In the dynamic world of chip development, modeling and simulation have emerged as indispensable tools, tackling the challenges posed by tighter process specifications, shrinking process windows, and cutthroat competition to introduce groundbreaking technologies to the market.
The journey from chip design to high-volume manufacturing involves countless engineering hours dedicated to perfecting various processes such as lithography, etching, deposition, and CMP, among others, all with the goal of achieving high yield. Astonishingly, the fabrication of a single device may require up to 1,000 individual tool steps. Yet, the primary hurdle for engineers lies in meeting process specifications with nanometer-level precision, which can significantly prolong development timelines and inflate costs.
“With the advent of 3D and EUV lithography, the challenges have only intensified,” remarks Keren Kanarik, technical managing director at Lam Research. Lam Research, a leading semiconductor equipment manufacturer, estimates that the development process for a specific target can cost over a hundred thousand dollars in process tool time and metrology work alone.
This article sheds light on three key processes where human expertise, combined with cutting-edge computing technologies, has proven instrumental in reducing process development costs and achieving faster time-to-target.
- Striking a Balance: Engineers vs. Machine Learning Algorithms
Inspired by the legendary chess match between Garry Kasparov and IBM’s Deep Blue, Lam Research engineers devised a competition to find the optimal balance between human effort and computational efficiency. In this case, the competition centered around a straightforward silicon dioxide etching process. Engineers compared the cost-to-target between a senior engineer’s approach and three machine learning algorithms.
Kanarik emphasizes, “Humans are our benchmark. We get the best results when combining human guidance with computer decision-making.” By leveraging this hybrid approach, the process development cost was successfully reduced from $105,000 to $52,000.
- Unlocking the Potential of Multi-Physics Modeling: Wafer Cleaning Process
Wafer cleaning is a critical step in chip manufacturing, with single-wafer cleaning processes offering superior uniformity compared to batch cleaning methods. However, the emergence of watermark defects posed a perplexing challenge. To address this issue, engineers at TEL (Tokyo Electron Limited) employed multi-physics modeling to gain insight into the specific tool parameters causing the defects.
Through a comprehensive modeling approach, TEL engineers discovered that water vapor absorption during the drying process led to the formation of watermarks on the wafers. By developing a model based on differential equations, the team successfully identified the conditions responsible for watermark formation and optimized the airflow in the chamber to eliminate the problem.
- Tackling Thermal Challenges in 3D-IC Systems: Multi-Physics Modeling
Thermal management has become a crucial consideration in the design of 3D-IC systems, where the integration of multiple chips introduces thermal and mechanical complexities. To address these challenges, multi-physics solvers have proven invaluable in accurately simulating system operation.
By combining chip thermal models, power models, signal models, and electrostatic models, engineers can gain a holistic understanding of thermal behavior and design robust cooling solutions. Early consideration of thermal resilience during the design phase is essential, as thermal and mechanical issues increase with the proximity of chiplets or packaged dies.
Looking Ahead: A Synergistic Future
While human expertise remains paramount in process development, the adoption of computer-aided solutions is steadily increasing. Machine learning’s application to process development is still in its infancy but holds immense promise for the industry.
Kanarik envisions a future where domain knowledge is effectively integrated into algorithms, enabling faster knowledge transfer and fundamentally transforming the way semiconductor processes are developed.
