NASA’s Jet Propulsion Laboratory (JPL) has chosen Microchip to design and build the High Performance Spaceflight Computer (HPSC) microprocessor, which is based on eight RISC-V X280 cores from SiFive and has additional RISC-V cores for general-purpose computing. The goal of the project is to develop a computer with “at least 100 times the computational capacity compared to current spaceflight computers.” The HPSC will not only be suitable for use in spacecraft, but also for a variety of applications on Earth, such as industrial robotics, medical equipment, defense, and commercial aviation. The chip will be designed to be fault tolerant, radiation tolerant, and secure, with initial availability expected in 2024 and space-qualified hardware available in 2025.

The HPSC is being developed as a solution for NASA’s mission to put autonomy into future spacecraft. The four main tasks associated with autonomy are sensing, perceiving, deciding, and actuating. These tasks include remote imaging, decision making, experiment management, and communication. NASA’s simulations suggest that the HPSC will increase computing performance by 1000 times compared to the current processors used in space, and the performance is expected to improve further with optimization of the software stack.

Compared to the current space-based computing systems, the HPSC represents a major upgrade. The rovers on Mars, Curiosity and Perseverance, are based on the RAD750 microprocessor from BAE Systems, which uses the 32-bit PowerPC 750 architecture and has a clock rate of 200 MHz. The Hubble Space Telescope, on the other hand, uses an even older 18-bit NSSC-1 system from the 1980s. An expert in space-based computing has described the HPSC as “exciting” and a much-needed improvement over the limited computing platforms currently in use in space.