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UCIe: The Future of Chiplet Interconnect

UCIe, or Universal Chiplet Interconnect Express, is a new specification that standardizes the connection between individual chiplets within a package. This allows for an open chiplet ecosystem and seamless communication at the package level.

A chiplet is a small integrated circuit with a specific, well-defined function. They can be thought of as building blocks for larger structures, similar to LEGO bricks.

The chiplet-based design approach is becoming increasingly popular as it allows for the combination of chiplets from different process nodes within the same package, resulting in cost savings for specialized chips. UCIe enables the creation of large SOCs that exceed the maximum reticle size. It also allows for the mixing of components from different vendors within the same package and improves manufacturing yields by using smaller dies.

Possible combinations of disaggregated Chiplets

UCIe is designed as a generic protocol for on-chip data transmission and has a common physical layer that can support multiple protocols. The architecture of UCIe is divided into three layers: Physical, Die-to-Die Adapter, and Protocol. The Physical layer supports multiple lanes with varying speeds and the Protocol layer can include CXL, PCIe, or proprietary Streaming protocols for data transfer between chiplets.

UCIe Layers and Components

The main features of UCIe include a high-speed interface, compatibility with multiple protocols, and a chiplet-based design for improved yields. Cadence Verification IP for UCIe is available to support the latest specification and allows for the simulation of different layers for IP, SOC, and system-level design verification. Semiconductor companies can use it for functional verification and achieve closure on their design in a timely manner.

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